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Configurable, Dual 2 A/Single 4 A, Synchronous Step-Down DC-to-DC Regulator
ADP2114
FEATURES
Configurable 2 A/2 A or 3 A/1 A dual output load combinations or 4 A combined single output High efficiency: up to 95% Input voltage VIN: 2.75 V to 5.5 V Selectable fixed output: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V or adjustable output voltage to 0.6 V minimum 1.5% accurate reference voltage Selectable switching frequency: 300 kHz, 600 kHz, 1.2 MHz or synchronized from 200 kHz to 2 MHz Optimized gate slew rate for reduced EMI External synchronization input or internal clock output Dual-phase, 180 phase shifted PWM channels Current mode for fast transient response Pulse skip under light load or forced PWM operation Input undervoltage lockout (UVLO) Independent enable inputs and PGOOD outputs Overcurrent and thermal overload protection Externally programmable soft start 32-lead 5 mm x 5 mm LFCSP package
TYPICAL APPLICATION CIRCUIT
VIN = 5V 10 100k 1F EN2 VIN4 VIN5 PGOOD2 VOUT2 = 1.8V, 2A 2.2H VIN6 PGOOD2 SW3 SW4 22F 47F PGND3 PGND4 FB2 V2SET SYNC/CLKOUT 22k 1.2nF
FREQ OPCFG SCFG GND
100k EN1 VIN1 VIN2 VIN3 PGOOD1 SW1 SW2 47F
VDD
22F
22F PGOOD1 4.7H VOUT1 = 3.3V, 2A
ADP2114
PGND1 PGND2 FB1 V1SET COMP1 SS1 47k
SYNC
15k
10nF
COMP2 SS2
10nF
22k 1.2nF
8.2k
fSW = 600kHz
Figure 1.
APPLICATIONS
Point of load regulation Telecommunications and networking systems Consumer electronics Industrial and Instrumentation Medical
GENERAL DESCRIPTION
The ADP2114 is a versatile, synchronous step-down, switching regulator that satisfies a wide range of customer point-of-load requirements. The two PWM channels can be configured to deliver independent outputs at 2 A and 2 A (or 3 A/1 A) or can be configured as a single interleaved output capable of delivering 4 A. The two PWM channels are 180 phase shifted to reduce input ripple current and to reduce input capacitance. The ADP2114 provides high efficiency and operates at switching frequencies of up to 2 MHz. At light loads, the ADP2114 can be set to operate in pulse skip mode for higher efficiency or in forced PWM mode to reduce EMI. The ADP2114 is designed with an optimized gate slew rate to reduce EMI emissions, allowing it to power sensitive, high performance signal chain circuits. The switching frequency can be set to 300 kHz, 600 kHz, or 1.2 MHz and can be synchronized to an external clock that minimizes the system noise. The bidirectional synchronization pin is also configurable as a 90 out-of-phase output clock, providing the possibility for a stackable multiphase power solution.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
The ADP2114 input voltage range is from 2.75 V to 5.5 V, and it converts to fixed outputs of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V that can be set independently for each channel using external resistors. Using a resistor divider, it is also possible to set the output voltage as low as 0.6 V. The ADP2114 operates over the -40C to +125C junction temperature range.
100 VIN = 3.3V; VOUT = 1.8V 95 VIN = 5.0V; VOUT = 3.3V
EFFICIENCY (%)
90
85
80 VIN = 5.0V; VOUT = 1.8V 75
0.1
1
3
LOAD CURRENT (A)
Figure 2. Typical Efficiency vs. Load Current
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
08143-002
70 0.01
08143-001
ADP2114 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 8 Supply Current ............................................................................ 13 Load Transient Response........................................................... 14 Bode Plots .................................................................................... 19 Simplified Block Diagram ............................................................. 20 Theory of Operation ...................................................................... 21 Control Architecture .................................................................. 21 Undervoltage Lockout (UVLO) ............................................... 21 Enable/Disable Control ............................................................. 21 Soft Start ...................................................................................... 21 Power Good................................................................................. 22 Pulse Skip Mode ......................................................................... 22 Hiccup Mode Current Limit ..................................................... 23 Thermal Overload Protection................................................... 23 Maximum Duty Cycle Operation ............................................ 23 Synchronization .......................................................................... 23 Converter Configuration ............................................................... 24 Selecting the Output Voltage .................................................... 24 Setting the Oscillator Frequency .............................................. 25 Synchronization and CLKOUT ................................................ 25 Operation Mode Configuration ............................................... 26 External Components Selection ................................................... 27 Input Capacitor Selection .......................................................... 27 VDD RC Filter ............................................................................ 27 Inductor Selection ...................................................................... 27 Output Capacitor Selection....................................................... 28 Control Loop Compensation .................................................... 28 Design Example .............................................................................. 30 Channel 1 Configuration and Components Selection .......... 30 Channel 2 Configuration and Components Selection .......... 31 System Configuration ................................................................ 32 Application Circuits ....................................................................... 33 Power Dissipation, Thermal Considerations .............................. 35 Circuit Board Layout Recommendations ................................... 36 Outline Dimensions ....................................................................... 37 Ordering Guide .......................................................................... 37
REVISION HISTORY
7/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 40
ADP2114 SPECIFICATIONS
If unspecified, VDD = VINx = EN1 = EN2 = 5.0 V. The minimum and maximum specifications are valid for TJ = -40C to +125C, unless otherwise specified. Typical values are at TJ = 25C. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Table 1.
Parameter POWER SUPPLY VDD Bias Voltage Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Quiescent Current Symbol VDD UVLO Conditions Min 2.75 VDD rising VDD falling EN1 = VDD = 5 V, EN2 = GND, VFB1 = VDD, OPCFG = GND EN2 = VDD = 5V, EN1 = GND, VFB2 = VDD, OPCFG = GND EN1 = EN2 = VDD = 5 V, VFB2 = VFB1 = VDD, OPCFG = GND EN1 = EN2 = GND, VDD = VINx = 2.75 V to 5.5 V, TJ = -40C to +115C Adjustable output, VFBx = 0.6 V, V1SET, V2SET = VDD or via 82 k to GND Fixed output; VFBx = 1.2 V, V1SET, V2SET via 4.7 k to GND 2.35 2.65 2.47 0.18 1.7 1.7 3.0 1.0 Typ Max 5.5 2.75 Unit V V V mA mA mA A
IDDCh1 IDDCh2 IDDCh1 + Ch2
2.5 2.5 4.0 10
Shutdown Current ERROR INTEGRATOR (OTA) FB1, FB2 Input Bias Current
IDDSD
IFB
1 11 550
65 15
nA A A/V V V V V V %
Transconductance COMPx VOLTAGE RANGE COMPx Zero-Current Threshold COMPx Clamp High Voltage COMPx Clamp Low Voltage OUTPUT CHARACTERISTICS Output Voltage Accuracy
gM VCOMP, ZCT VCOMP, HI VCOMP, LO VFB Guaranteed by design VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 2.75 V to 5.5 V Adjustable output, TJ = 25C, V1SET, V2SET = VDD or via 82 k to GND Adjustable output, TJ = -40C to +125C, V1SET, V2SET = VDD or via 82 k to GND Fixed output, TJ = 25C, V1SET, V2SET = GND or via 4.7 k, 8.2 k, 15 k, 27 k, 47 k to GND Fixed output, TJ = -40C to +125C, V1SET, V2SET = GND or via 4.7 k, 8.2 k, 15 k, 27 k, 47 k to GND VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 2.75 V to 5.5 V All oscillator parameters provided for VDD = 2.75 V to 5.5 V FREQ tied to GND FREQ via 8.2 k to GND FREQ via 27 k to GND fSYNC = 2 x fSW FREQ tied to GND FREQ via 8.2 k to GND FREQ via 27 k to GND
0.65 0.597 0.594 -1.0
1.12 2.36 0.70 0.600 0.600
2.45
0.603 0.606 +1.0
VFB ERROR
-1.5
+1.5
%
Line Regulation Load Regulation OSCILLATOR Switching Frequency fSW
0.05 0.03
%/V %/A
255 510 1020 400 800 1600 100
300 600 1200
345 690 1380 1000 2000 4000
kHz kHz kHz kHz kHz kHz ns
SYNC Frequency Range
fSYNC
SYNC Input Pulse Width
Rev. 0 | Page 3 of 40
ADP2114
Parameter SYNC Pin Capacitance to GND SYNC Input Logic Low SYNC Input Logic High Phase Shift Between Channels CLKOUT Frequency Symbol CSYNC VIL_SYNC VIH_SYNC fCLKOUT Conditions Min Typ 5 Max 0.8 2.0 180 fCLKOUT = 2 x fSW FREQ tied to GND FREQ via 8.2 k to GND FREQ via 27 k to GND CCLKOUT = 20 pF All current limit parameters provided for VDD = VINx = 2.75 V to 5.5 V OPCFG tied to GND or via 4.7 k to GND OPCFG via 8.2 k or 15 k to GND OPCFG tied to GND or via 4.7 k to GND OPCFG via 8.2 k or 15 k to GND fSW = 300 kHz 510 1020 2040 100 600 1200 2400 10 690 1380 2760 Unit pF V V Degrees kHz kHz kHz ns ns
CLKOUT Positive Pulse Time CLKOUT Rise or Fall Time CURRENT LIMIT Peak Output Current Limit, Channel 1 Peak Output Current Limit, Channel 2 Current Sense Amplifier Gain Hiccup Time Number of Cumulative Current Limit Cycles to Go into Hiccup SWITCH NODE CHARACTERISTICS High-Side, P-Channel RDS ON 1 Low-Side, N-Channel RDS ON1 SWx Minimum On Time SWx Minimum Off Time SWx Maximum Leakage Current ENABLE INPUT EN1, EN2 Logic Low Level EN1, EN2 Logic High Level EN1, EN2 Input Leakage Current THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis SOFT START SS1, SS2 Pin Current Soft Start Threshold Voltage Soft Start Pull-Down Current POWER GOOD Overvoltage PGOODx Rising Threshold 2 Overvoltage PGOODx Falling Threshold2 Undervoltage PGOODx Rising Threshold2 Undervoltage PGOODx Falling Threshold2 PGOODx Delay PGOODx Leakage Current PGOODx Low Saturation Voltage
1 2
tCLKOUT
ILIMIT1 ILIMIT2 GCS
2.4 3.5 2.4 1.2 10
3.3 4.5 3.3 1.9 4 13.6 8
4.0 5.3 4.0 2.6 17
A A A A A/V ms Cycles
SWON MIN SWOFF MIN
VDD = VINx = 3.3 V VDD = VINx = 5.0 V VDD = VINx = 3.3 V VDD = VINx = 5.0 V VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 5.5 V VDD = VINx = 2.75 V VDD = VINx = 2.75 V to 5.5 V; ENx = GND, TJ = -40C to +115C VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 2.75 V to 5.5 V VDD = VINx = ENx = 2.75 V to 5.5 V, TJ = -40C to +115C
68 52 32 27 107 192 255 0.1
15
m m m m ns ns ns A
ENLOW ENHI IEN_LEAK
0.8 2 0.1 1
V V A
TTMSD
150 25 VDD = VINx = 2.75 V to 5.5 V; VSS = 0 V VDD = VINx = 2.75 V to 5.5 V VDD = VINx = 2.75 V to 5.5 V; EN = GND All power good parameters provided for VDD = VINx = 2.75 V to 5.5 V 4.8 0.5 6.0 0.65 7.8
C C A V mA
ISS1, ISS2 VSS_THRESH
100 85
VPGOODx = VDD IPGOODx = 1 mA
116 108 92 84 50 0.1 50
114 97
1 110
% % % % s A mV
Pin-to-pin measurements. The thresholds are expressed in percentage terms of the nominal output voltage. Rev. 0 | Page 4 of 40
ADP2114 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VDD to GND VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to PGND1, PGND2, PGND3, PGND4 EN1, EN2, SCFG, FREQ, FB1, FB2, SYNC/ CLKOUT, PGOOD1, PGOOD2, V1SET, V2SET, COMP1, COMP2, SS1, SS2 to GND FB1, FB2 to GND SW1, SW2, SW3, SW4 to PGND1, PGND2, PGND3, PGND4 PGND1, PGND2, PGND3, PGND4 to GND VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to VDD JA, JEDEC 1S2P PCB, Natural Convection Operating Junction Temperature Range Storage Temperature Range Maximum Soldering Lead Temperature (10 sec) Rating -0.3 V to +6 V -0.3 V to +6 V -0.3 V to (VDD + 0.3 V)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination.
-0.3V to +3.6V -0.3 V to (VDD + 0.3 V) 0.3 V 0.3 V 34C/W -40C to +125C -65C to +150C 260C
ESD CAUTION
Rev. 0 | Page 5 of 40
ADP2114 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FB1 V1SET SS1 PGOOD1 EN1 VIN1 VIN2 VIN3 32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
GND COMP1 FREQ SCFG SYNC/CLKOUT OPCFG COMP2 VDD
1 2 3 4 5 6 7 8
ADP2114
TOP VIEW (Not to Scale)
THERMAL PAD
SW1 SW2 PGND1 PGND2 PGND3 PGND4 SW3 SW4
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 Mnemonic GND COMP1 FREQ SCFG SYNC/CLKOUT Description Ground for the Internal Analog and Digital Circuits. Connect GND to the signal/analog ground plane before connecting to the power ground. Error Amplifier Output for Channel 1. Connect a series RC network from COMP1 to GND to compensate for Channel 1. For multiphase operation, tie COMP1 and COMP2 together. Frequency Select Input. Connect this pin through a resistor to GND to set the appropriate switching frequency (see Table 5). Synchronization Configuration Input. SCFG configures the SYNC/CLKOUT pin as an input or output. Tie this pin to VDD to configure SYNC/CLKOUT as an output. Tie this pin to GND to configure SYNC/CLKOUT as an input. This is a configurable bidirectional pin (configured with the SCFG pin--see the Pin 4 description for details). When SYNC/CLKOUT is an output, a buffered clock of twice the switching frequency with a phase shift of 90 is available on this pin. When configured as an input, this pin accepts an external clock to which the converters are synchronized. The frequency select resistor, mentioned in the description of Pin 3, must be selected close to the expected switching frequency for stable operation. Operation Configuration Input. Connect this pin through a resistor to GND to set the system mode of operation according to Table 7. This pin can be used to select a peak current limit for each power channel and enable or disable the pulse skip mode. Error Amplifier Output for Channel 2. Connect a series RC network from COMP2 to GND to compensate the Channel 2. Tie COMP1 and COMP2 together for multiphase configuration. Power Supply Input. The power source for the ADP2114 internal circuitry. Connect VDD and VINx with a 10 resistor as close as possible to the ADP2114. Bypass VDD to GND with a 1 F or greater capacitor. Feedback Voltage Input for Channel 2. For the fixed output voltage option, connect FB2 to VOUT2. For the adjustable output voltage option, connect this pin to a resistor divider between VOUT2 and GND. The reference voltage for the adjustable output voltage option is 0.6 V. With multiphase configurations, connect FB2 to FB1 and then connect them to VOUT. Output Voltage Set Pin for Channel 2. Connect this pin through a resistor to GND or tie to VDD to select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V) or an adjust output voltage for VOUT2. See Table 4 for output voltage selection. Soft Start Input for Channel 2. Place a capacitor from SS2 to GND to set the soft start period. A 10 nF capacitor sets a 1 ms soft start period. For multiphase configuration, connect SS2 to SS1. Open-Drain Power Good Output for Channel 2. Place a 100 k pull-up resistor to VDD or any other voltage 5.5 V; PGOOD2 pulls low when Channel 2 is out of regulation. Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 converter and drive EN2 low to turn off Channel 2. Tie EN2 to VDD for startup with VDD. With multiphase configuration, tie EN2 to EN1.
6
OPCFG
7 8 9
COMP2 VDD FB2
10
V2SET
11 12 13
SS2 PGOOD2 EN2
Rev. 0 | Page 6 of 40
08143-003
NOTES 1. CONNECT THE EXPOSED THERMAL PAD TO THE SIGNAL/ANALOG GROUND PLANE.
FB2 V2SET SS2 PGOOD2 EN2 VIN4 VIN5 VIN6
9 10 11 12 13 14 15 16
ADP2114
Pin No. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Mnemonic VIN4 VIN5 VIN6 SW4 SW3 PGND4 PGND3 PGND2 PGND1 SW2 SW1 VIN3 VIN2 VIN1 EN1 PGOOD1 SS1 V1SET Description Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2. Tie SW3 to SW4 and then connect the output LC filter between SW and the output voltage. Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2. Tie SW3 to SW4 and then connect the output LC filter between SW and the output voltage. Power Ground. Source of the low-side internal power MOSFET of Channel 2. Power Ground. Source of the low-side internal power MOSFET of Channel 2. Power Ground. Source of the low-side internal power MOSFET of Channel 1. Power Ground. Source of the low-side internal power MOSFET of Channel 1. Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1. Tie SW1 to SW2 and connect the output LC filter between SW and the output voltage. Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1. Tie SW1 to SW2 and connect the output LC filter between SW and the output voltage. Power Supply Input. The source of the high-side internal power MOSFET of Channel 1. Power Supply Input. The source of the high-side internal power MOSFET of Channel 1. Power Supply Input. The source of the high-side internal power MOSFET of Channel 1. Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 converter and drive EN1 low to turn off Channel 1. Tie EN1 to VDD for startup with VDD. With multiphase configurations, connect EN1 to EN2. Open-Drain Power Good Output for Channel 1. Place a 100 k pull-up resistor to VDD or any other voltage 5.5 V; PGOOD1 pulls low when Channel 1 is out of regulation. Soft Start Input for Channel 1. Place a capacitor from SS1 to GND to set the soft start period. A 10 nF capacitor sets a 1 ms soft start period. For multiphase configuration, connect SS1 to SS2. Output Voltage Set Pin for Channel 1. Connect this pin through a resistor to GND or tie to VDD to select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V) or an adjustable output voltage for VOUT1. See Table 4 for output voltage selection. Feedback Voltage Input for Channel 1. For the fixed output voltage option, connect FB1 to VOUT1. For the adjusted output voltage option, connect this pin to a resistor divider between VOUT1 and GND. With multiphase configurations, connect FB1 to FB2 and then connect them to VOUT. Exposed Thermal Pad. Connect to the signal/analog ground plane.
32
FB1
EPAD (EP)
Rev. 0 | Page 7 of 40
ADP2114 TYPICAL PERFORMANCE CHARACTERISTICS
100 95 90
EFFICIENCY (%)
100 95 90
EFFICIENCY (%)
85 80 75 70 65 60 10 VOUT = 3.3V VOUT = 3.3V; PULSE SKIP VOUT = 1.8V VOUT = 1.8V; PULSE SKIP
08143-004
85 80 75 70 65 60 10 VIN = 5V, VOUT = 2.5V FORCED PWM VIN = 5V, VOUT = 2.5V PULSE SKIP VIN = 3.3V, VOUT = 1.2V FORCED PWM VIN = 3.3V, VOUT = 1.2V PULSE SKIP 100 1k 10k LOAD CURRENT (mA)
08143-006 08143-007
100
1k
10k
LOAD CURRENT (mA)
Figure 4. Channel 1 Efficiency vs. Load, VIN = 5 V and fsw = 300 kHz; VOUT = 3.3 V, Inductor Cooper Bussmann DR1050-8R2-R, 8.2 H, 15 m; VOUT = 1.8 V, Inductor TOKO FDV0620-4R7M, 4.7 H, 53 m
100 95 90
EFFICIENCY (%)
Figure 6. Efficiency vs. Load at fSW = 1.2 MHz; Inductor TOKO FDV0620-1R0M, 1.0 H, 14 m
90
85 VIN = 3.3V
EFFICIENCY (%)
85 80 75 70 65 60 10 VOUT = 3.3V VOUT = 3.3V; PULSE SKIP VOUT = 1.8V VOUT = 1.8V; PULSE SKIP 100 1k 10k
08143-005
80 VIN = 5V 75
70
65
60 100
1k LOAD CURRENT (mA)
10k
LOAD CURRENT (mA)
Figure 5. Channel 2 Efficiency vs. Load, VIN = 5 V and fSW = 600 kHz; VOUT = 3.3 V, Inductor TOKO FDV0620-4R7M, 4.7 H, 53 m; VOUT = 1.8 V, Inductor TOKO FDV0620-2R2M, 2.2 H, 30 m
Figure 7. Efficiency Combined Dual-Phase Output, VOUT = 0.8 V and fSW = 1.2 MHz; Inductor TOKO FDV0620-1R0M, 1.0 H, 14 m
Rev. 0 | Page 8 of 40
ADP2114
0.50
0.50
VOUT ERROR, NORMALIZED (%)
0.25
VOUT ERROR, NORMALIZED (%)
08143-008
0.25
0
0
-0.25
-0.25
0
500
1000
1500
2000
2500
3000
0
500
1000 LOAD CURRENT (mA)
1500
2000
LOAD CURRENT (mA)
Figure 8. Load Regulation, Channel 1: VIN = 5 V, fSW = 600 kHz, and TA = 25C
0.5 0.4
VOUT ERROR, NORMALIZED (%)
Figure 11. Load Regulation, Channel 2: VIN = 5 V, fSW = 300 kHz, and TA = 25C
0.5 0.4
VOUT ERROR, NORMALIZED (%)
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
08143-009
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
Figure 9. Line Regulation, Channel 1: Load Current = 3 A and fSW = 600 kHz
1.00 0.75 0.50
VOUT ERROR (%)
Figure 12. Line Regulation, Channel 2: Load Current = 1 A and fSW = 600 kHz
1.00 0.75 0.50
VOUT ERROR (%)
0.25 VIN = 5.5V, NO LOAD 0 -0.25 -0.50 -0.75 -1.00 -50 VIN = 2.75V; 3A LOAD
0.25 VIN = 5.5V, NO LOAD 0 -0.25 -0.50 -0.75 -1.00 -50 VIN = 2.75V; 2A LOAD
08143-010
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 10. Output Voltage vs. Temperature, Channel 1: VOUT = 0.6 V and fSW = 600 kHz
Figure 13. Output Voltage vs. Temperature, Channel 2: VOUT = 1.5 V and fSW = 600 kHz
Rev. 0 | Page 9 of 40
08143-013
08143-012
-0.5 2.5
-0.5 2.5
08143-011
-0.50
-0.50
ADP2114
250 225 200 175
310
fSW = 300kHz fSW = 600kHz fSW = 1.2MHz
330
320
MINIMUM ON-TIME (ns)
fSW (kHz)
08143-014
150 125 100 75 50 2.5
300
290
280
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
Figure 14. Minimum On-Time, Open Loop, Includes Dead Time
350 330 310
MINIMUM OFF-TIME (ns)
Figure 17. Switching Frequency vs. Input Voltage, fSW = 300 kHz
660
fSW = 300kHz fSW = 600kHz fSW = 1.2MHz
640
290
620
250 230 210 190 170
08143-015
fSW (kHz)
270
600
580
560
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
Figure 15. Minimum Off-Time, Open Loop, Includes Dead Time
120
Figure 18. Switching Frequency vs. Input Voltage, fSW = 600 kHz
80 70 60
100
80
NMOS RDS ON (m)
PMOS RDS ON (m)
50 40 30 20 10 0 2.5 +125C +115C +85C +25C -40C 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5
08143-019
60
40 +125C +115C +85C +25C -40C 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5
08143-016
20
0 2.5
Figure 16. High-Side PMOS Resistance vs. Input Voltage, Includes Bond Wires
Figure 19. Low-Side NMOS Resistance vs. Input Voltage, Includes Bond Wires
Rev. 0 | Page 10 of 40
08143-018
150 2.5
540 2.5
08143-017
270 2.5
ADP2114
330
2.0 1.9
ENABLE/DISABLE THRESHOLD (V)
320
1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 ENABLE; VIN = 5.5V ENABLE; VIN = 2.75V DISABLE; VIN = 5.5V DISABLE; VIN = 2.75V
310
VIN = 2.75V VIN = 5.5V
fSW (kHz)
300
290
280
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 20. Switching Frequency vs. Temperature, fSW = 300 kHz
660
Figure 23. Enable/Disable Threshold vs. Temperature
2.8
640
2.7
UVLO THRESHOLD (V)
VDD RISING
620
VIN = 2.75V VIN = 5.5V
fSW (kHz)
2.6
600
2.5 VDD FALLING 2.4
580
560
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 21. Switching Frequency vs. Temperature, fSW = 600 kHz
1300 1280 1260 1240
Figure 24. UVLO Threshold vs. Temperature
1300 1280 1260 1240
VIN = 2.75 V
1200 1180 1160 1140 1120 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5
08143-022
fSW (kHz)
fSW (kHz)
1220
1220 1200 1180 1160 1140 1120 -25 0 25 50 75 100 125
08143-025
VIN = 5.5 V
1100 2.5
1100 -50
TEMPERATURE (C)
Figure 22. Switching Frequency vs. Input Voltage, fSW = 1.2 MHz
Figure 25. Switching Frequency vs. Temperature, fSW = 1.2 MHz
Rev. 0 | Page 11 of 40
08143-024
08143-021
540 -50
2.3 -50
08143-023
08143-020
270 -50
0.8 -50
ADP2114
120 OVERVOLTAGE; VOUT RISING 115
PGOOD THRESHOLD (%)
6.0 5.5 5.0 OVERVOLTAGE; VOUT FALLING
CURRENT LIMIT (A)
110 105 100 95 90 85 80 -50
4.5 4.0 3.5 3.0 2.5 2.0 1.5
3A OPTION
2A OPTION
UNDERVOLTAGE; VOUT RISING
1A OPTION
UNDERVOLTAGE, VOUT FALLING
1.0 0.5
08143-026
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 26. PGOOD Threshold vs. Temperature
10 9 8
SHUTDOWN CURRENT (A)
Figure 29. Peak Current Limit vs. Temperature, VIN = 5 V
700 650 600
7
VIN = 5.5V
gm (A/V)
6 5 4 3 2 1
08143-027
550 500 450 400 VIN = 2.75V
VIN = 5.5V
VIN = 2.75V
350 300 -50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 27. Shutdown Current vs. Temperature
5
Figure 30. gM vs. Temperature
4
VDD CURRENT (mA)
3
VIN = 5.5V
2
VIN = 2.75V
1
-25
0
25
50
75
100
125
TEMPERATURE (C)
Figure 28. VDD Input Current vs. Temperature (Not Switching)
08143-028
0 -50
Rev. 0 | Page 12 of 40
08143-030
0 -50
08143-029
0 -50
ADP2114
SUPPLY CURRENT
5.0 4.5 4.0
VDD CURRENT (mA)
5.0 4.5 FORCED PWM 4.0
VDD CURRENT (mA)
3.5 3.0 2.5 2.0 1.5 1.0 2.5 PULSE SKIP
3.5 3.0 2.5 PULSE SKIP 2.0 1.5 1.0 2.5
FORCED PWM
08143-031
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD VOLTAGE (V)
VDD VOLTAGE (V)
Figure 31. VDD Supply Current, No Load, Channel 1: VOUT = 1.5 V, Channel 2 Off, fSW = 1.2 MHz
5.0 4.5 4.0
VDD CURRENT (mA)
Figure 33. VDD Supply Current, No Load, Channel 1: VOUT = 1.5 V, Channel 2: VOUT = 0.8 V, fSW = 1.2 MHz
5.0 4.5 4.0
VDD CURRENT (mA)
VDD = 5.5V, FORCED PWM
VDD = 2.75V, FORCED PWM
3.5 3.0 FORCED PWM 2.5 2.0 PULSE SKIP 1.5 1.0 2.5
3.5 3.0 2.5 VDD = 2.75V, PULSE SKIP 2.0 1.5 1.0 -50
VDD = 5.5V PULSE SKIP
3.0
3.5
4.0
4.5
5.0
5.5
08143-032
-25
0
25
50
75
100
125
VDD VOLTAGE (V)
TEMPERATURE (C)
Figure 32. VDD Supply Current, No Load, Channel 2: VOUT = 0.8 V, Channel 1 Off, fSW = 1.2 MHz
Figure 34. VDD Supply Current vs. Temperature, Channel 1: VOUT = 1.5 V, Channel 2: VOUT = 0.8 V, fSW = 1.2 MHz
Rev. 0 | Page 13 of 40
08143-034
08143-033
ADP2114
LOAD TRANSIENT RESPONSE
VOUT
2
2
VOUT
IOUT IOUT
4
SW
4
SW
1
08143-035
3
CH1 5.0V
CH2 50mV CH4 2.0A
M200s 50MS/s 200ns/pt
A CH2
-33mV
CH3 5.0V
CH2 50mV CH4 1.0A
M200s 50MS/s 20ns/pt
A CH2
-34mV
Figure 35. Channel 1: VIN = 5 V, VOUT = 3.3V, fSW = 600 kHz; Forced PWM (See Table 12 for the Circuit Details)
Figure 38. Channel 2: VIN = 5 V, VOUT = 1.8 V, fSW = 600 kHz; Pulse Skip (See Table 12 for the Circuit Details)
VOUT
2 2
VOUT
IOUT
4
IOUT SW
4
SW
3
08143-036
1
CH3 5.0V
CH2 50mV CH4 2.0A
M200s 50MS/s 200ns/pt
A CH2
-23mV
CH1 5.0V
CH2 10mV CH4 2.0A
M200s 12.5MS/s 80ns/pt
A CH4
960mA
Figure 36. Channel 2: VIN = 5 V, VOUT = 1.8 V, fSW = 600 kHz; Forced PWM (See Table 12 for the Circuit Details)
Figure 39. Channel 1: VIN = 3.3 V, VOUT = 1.2 V, fSW = 1.2 MHz; Forced PWM (See Table 12 for the Circuit Details)
2
2
VOUT
VOUT
IOUT
4
IOUT SW
SW
4
1
08143-037
1
CH1 5.0V
CH2 10mV CH4 2.0A
M200s 12.5MS/s A CH4 80ns/pt
960mA
CH1 5.0V
CH2 10mV CH4 2.0A
M200s 12.5MS/s 80ns/pt
A CH4
960mA
Figure 37. Channel 1: VIN = 5 V, VOUT = 1.2 V, fSW = 1.2 MHz; Forced PWM (See Table 12 for the Circuit Details)
Figure 40. Channel 1: VIN = 3.3 V, VOUT = 1.2 V, fSW = 1.2 MHz; Pulse Skip (See Table 12 for the Circuit Details)
Rev. 0 | Page 14 of 40
08143-040
08143-039
08143-038
ADP2114
2
VOUT
2
VOUT
VIN VIN
SW
1 3 1 3
SW
08143-041
CH1 5.0V CH3 1.0V
CH2 10mV
M400s
A CH3
4.86V
CH1 5.0V CH3 1.0V
CH2 10mV
M400s
A CH3
3.50V
Figure 41. 3.3 V to 5 V Line Transient, VOUT = 1.5 V, Load = 1 A fSW = 1.2 MHz, Pulse Skip Enabled
2
Figure 44. 5 V to 3.3 V Line Transient, VOUT = 1.5 V, Load = 1 A fSW = 1.2 MHz, Forced PWM
VOUT
VOUT
2
VIN VIN SW SW
1 1 3 3
08143-042
CH1 5.0V CH3 1.0V
CH2 10mV
M400s
A CH3
3.58V
CH1 2.0V CH3 1.0V
CH2 10mV
M400s
A CH3
4.82V
Figure 42. 5 V to 3.3 V Line Transient, VOUT = 1.5 V, Load = 1 A fSW = 1.2 MHz, Pulse Skip Enabled
Figure 45. 3.3 V to 5 V Line Transient, VOUT = 0.6 V, Load = 1 A fSW = 600 kHz, Pulse Skip Enabled
VOUT
2
VOUT
2
VIN
VIN
SW
SW
1 1 3 3
08143-043
CH1 5.0V CH3 1.0V
CH2 10mV
M400s
A CH3
4.84V
CH1 2.0V CH3 1.0V
CH2 10mV
M400s
A CH3
3.62V
Figure 43. 3.3 V to 5 V Line Transient, VOUT = 1.5 V, Load = 1 A fSW = 1.2 MHz, Forced PWM
Figure 46. 5 V to 3.3 V Line Transient, VOUT = 0.6 V, Load = 1 A fSW = 600 kHz, Pulse Skip Enabled
Rev. 0 | Page 15 of 40
08143-046
08143-045
08143-044
ADP2114
VOUT, AC VOUT
2 2
SW
VIN SW
3
INDUCTOR CURRENT
1 3
4
08143-047
CH1 2.0V CH3 1.0V
CH2 10mV
M400s
A CH3
4.84V
CH3 2.0V
CH2 20mV CH2 500mA
M1s
A CH3
2.52V
Figure 47. 3.3 V to 5 V Line Transient, VOUT = 0.6 V, Load = 1 A fSW = 600 kHz, Forced PWM
VOUT
2
Figure 50. Forced PWM Mode, CCM Operation, 200 mA Load, fSW = 600 kHz
VOUT, AC
2
VIN
SW
SW
3
INDUCTOR CURRENT
1 3
4
08143-048 08143-051 08143-052
CH1 2.0V CH3 1.0V
CH2 10mV
M400s
A CH3
3.50V
CH3 2.0V
CH2 20mV CH2 500mA
M1s
A CH3
4.32V
Figure 48. 5 V to 3.3 V Line Transient, VOUT = 0.6 V, Load = 1 A fSW = 600 kHz, Forced PWM
VOUT, AC
2
Figure 51. Pulse Skip Enabled, DCM Operation, 200 mA Load, fSW = 600 kHz
EN2
1
SW
2
VOUT2
3 4
SS2 INDUCTOR CURRENT
4 3
08143-049
SW
CH3 2.0V
CH2 10mV CH4 500mA
M4s
A CH3
4.32V
CH1 5.0V CH3 5.0V
CH2 1.0V CH4 2.0V
M1.0ms
A CH1
2.4V
Figure 49. Pulse Skip Mode, 110 mA Load
Figure 52. Soft Start, Channel 2 VOUT = 1.8 V, CSS2 = 10 nF
Rev. 0 | Page 16 of 40
08143-050
ADP2114
INDUCTOR CURRENT EN2
1
VOUT2
4
2
4
SS2
2
VOUT
SW
3 3
08143-053
SW CH2 1.0V CH4 2.0A M2.0ms A CH4 1.72V
08143-056 08143-058 08143-057
CH1 5.0V CH3 5.0V
CH2 1.0V CH4 500mV
M200s
A CH1
2.4V
CH3 5.0V
Figure 53. Start with Precharged Output
Figure 56. Hiccup Mode, fSW = 600 kHz, 6.8 ms Hiccup Cycle
INDUCTOR CURRENT INDUCTOR CURRENT
4 4
VOUT2
2 2
VOUT
3
SW CH2 1.0V CH4 2.0A M1.0ms A CH2 1.12V
08143-054
3
SW CH2 1.0V CH4 2.0A M2.0ms A CH2 1.12V
CH3 5.0V
CH3 5.0V
Figure 54. Current Limit Entry, Channel 2 VOUT = 1.8 V, 2 A Configuration, fSW = 600 kHz
Figure 57. Exit Hiccup Mode, Channel 2 VOUT = 1.8 V, fSW = 600 kHz
EXTERNAL SYNC INDUCTOR CURRENT
1 4
CHANNEL 1 SW VOUT2
2 4
CHANNEL 2 SW
3
SW CH2 1.0V CH4 2.0A M10.0s A CH2 1.12V
08143-055
3
CH3 5.0V
CH1 5.0V CH3 5.0V
M1.0s CH4 5.0V
A CH1
3.0V
Figure 55. Current Limit Entry (Zoomed In), Channel 2 VOUT = 1.8 V, 2 A Configuration, fSW = 600 kHz
Figure 58. External Synchronization, fSYNC = 1.5 MHz, fSW = 750 kHz
Rev. 0 | Page 17 of 40
ADP2114
CHANNEL 1 SW
1 4 2
EN2
VOUT2 CHANNEL 2 SW
3
PGOOD2 INTERNAL CLKOUT
4
1 3
08143-059
SW
CH1 5.0V CH3 5.0V
M1.0s CH4 5.0V
A CH3
3.0V
CH1 5.0V CH3 5.0V
CH2 1.0V CH4 2.0V
M200s
A CH1
3.5V
Figure 59. Internal Clock Out, fSW = 600 kHz, fCLKOUT = 1.2 MHz
Figure 61. Power Good Signal
CHANNEL 1 SW
CHANNEL 3 SW
1 4 2 2 3
INDUCTOR CURRENT, PHASE 2
INDUCTOR CURRENT, PHASE 1
PHASE 2 SW CHANNEL 2 SW
4
3
CHANNEL 4 SW
08143-060
1
CH1 2.0V CH3 2.0V
CH2 2.0V CH4 2.0V
M1.0s
A CH1
2.0V
CH1 5.0V CH3 5.0V
CH2 1.0A CH4 1.0A
M1.0s
A CH1
1.9V
Figure 60. 4-Channel Operation, Two ADP2114s, One Synchronizes Another, 90 Phase-Shifted Switch Nodes
Figure 62. Combined Dual-Phase Output Operation, VOUT = 1.2 V, fSW = 1.1 MHz, 4 A Load
Rev. 0 | Page 18 of 40
08143-062
PHASE 1 SW
08143-061
ADP2114
BODE PLOTS
50 40 30 20 150 120 90 PHASE 60 30 0 MAGNITUDE -10 -20 -30 -40 -50 1k 10k
M1
MAGNITUDE (dB)
10 0
-30 -60 -90 -120 100k
M2
-150
FREQUENCY (Hz)
08143-063
FREQUENCY MAGNITUDE PHASE
M1
54.86kHz 0.042dB 50.099
M2
210.34kHz -19.632dB -0.412
M2 - M1
155.48kHz -19.673dB -50.511
Figure 63. VIN = 5 V, VOUT = 3.3 V, Load = 2 A, fSW = 600 kHz, Crossover Frequency (fCO) = 55 kHz; Phase Margin 50 (See Table 12 for the Circuit Details)
50 40 30 PHASE 20 48 24 MAGNITUDE 0 -24 -48 -72 -96 10k
M1
120 96 72
MAGNITUDE (dB)
10 0 -10 -20 -30 -40 -50 1k 100k
M2
-120 1M
FREQUENCY (Hz)
08143-064
FREQUENCY MAGNITUDE PHASE
M1
96.71kHz -0.075dB 53.305
M2
335.27kHz -17.371dB -0.389
M2 - M1
238.56kHz -17.296dB -53.694
Figure 64. VIN = 5 V, VOUT = 1.2 V, Load = 2 A, fSW = 1.2 MHz, Crossover Frequency (fCO) = 97 kHz; Phase Margin 53 (See Table 12 for the Circuit Details)
Rev. 0 | Page 19 of 40
PHASE (Degrees)
PHASE (Degrees)
ADP2114 SIMPLIFIED BLOCK DIAGRAM
VDD GND SCFG FREQ SYNC/CLKOUT UVLO UVLO PGOOD1
OSC
PHASE SHIFT
OSC_CH1 OSC_CH2 CLIM_CH1
0.7V
VFB1 VIN1 VIN2 VIN3
OPCFG
CURRENT LIMIT/ CONFIGURATION
CLIM_CH2 PULSE SKIP ENABLE 0.5V
EN1 COMP1 V1SET FB1 UVLO VOUT SELECTOR VFB1 SS1 - + + OSC_CH1 PULSE SKIP ENABLE OTSD
GATE CONTROL LOGIC AND MOSFET DRIVERS WITH ANTI-SHOOT THROUGH PROTECTION
PMOS
SW1 SW2
NMOS
ISS = 6A
gm ERROR
AMPLIFIER
PGND1 PGND2 HICCUP TIMER - + CLIM_CH1 CURRENT SENSE AMPLIFIER
VREF = 0.6V VDD SLOPE COMPENSATION/ RAMP GENERATOR
PWM COMPARATOR
POWER STAGE
CURRENT LIMIT COMPARATOR
CHANNEL 1
0.7V THERMAL SHUTDOWN OTSD
PGOOD2
VFB2 VIN4 VIN5 VIN6
0.5V
EN2 COMP2 V2SET FB2 UVLO VOUT SELECTOR VFB2 SS2 - + + OSC_CH2 PULSE SKIP ENABLE OTSD
GATE CONTROL LOGIC AND MOSFET DRIVERS WITH ANTI-SHOOT THROUGH PROTECTION
PMOS
SW3 SW4
NMOS
ISS = 6A
gm ERROR
AMPLIFIER
PGND3 PGND4 HICCUP TIMER - + CLIM_CH2 CURRENT SENSE AMPLIFIER
VREF = 0.6V VDD SLOPE COMPENSATION/ RAMP GENERATOR
PWM COMPARATOR
POWER STAGE
Figure 65. Simplified Block Diagram
Rev. 0 | Page 20 of 40
08143-065
CURRENT LIMIT COMPARATOR
CHANNEL 2
ADP2114 THEORY OF OPERATION
The ADP2114 is a high efficiency, dual, fixed switching frequency, synchronous step-down, dc-to-dc converter with flex mode architecture, which is the Analog Devices, Inc., proprietary version of its peak current mode control architecture. The device operates over an input voltage range of 2.75 V to 5.5 V. Each output channel provides an adjustable output down to 0.6 V and delivers up to 2 A of load current. When both the output channels are tied together, they operate 180 out of phase to deliver up to 4 A of load current. The integrated high-side, P-channel power MOSFET and the low-side, N-channel power MOSFET yield high efficiency at medium to heavy loads. Pulse skip mode is available for improved efficiency at light loads. With its high switching frequency (up to 2 MHz) and its integrated power switches, the ADP2114 has been optimized to deliver high performance in a small size for power management solutions. The ADP2114 also includes undervoltage lockout (UVLO) with hysteresis, soft start, and power good, as well as protection features such as output short-circuit protection and thermal shutdown. The output voltages, current limits, switching frequency, pulse skip operation, and soft start time are externally programmable with tiny resistors and capacitors.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO threshold is 2.65 V when VDD is increasing and 2.47 V when VDD is decreasing. The 180 mV hysteresis prevents the converter from turning off and on repeatedly during a slow voltage transition on VDD close to the 2.75 V minimum operational level due to changing load conditions.
ENABLE/DISABLE CONTROL
The EN1 and EN2 pins are used to independently enable or disable Channel 1 and Channel 2, respectively. Drive ENx high to turn on the corresponding channel of ADP2114. Drive ENx low to turn off the corresponding channel of ADP2114, reducing input current below 1 A. To force a channel to start automatically when input power is applied, connect the corresponding ENx to VDD. When shut down, the ADP2114 channels discharge the soft start capacitor, causing a new soft start cycle every time the converters are re-enabled.
SOFT START
The ADP2114 soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during startup. Soft start begins after the undervoltage lockout threshold is exceeded and the enable pin, EN1 (EN2), is pulled high above 2.0 V. External capacitors to ground are required on both the SS1 and SS2 pins. Each regulating channel has its own soft start circuit. When the converter powers up and is enabled, the internal 6 A current source charges the external soft start capacitor, establishing a voltage ramp slope at the SS1 (SS2) pin, as shown in Figure 66. The soft start time period ends when the soft start ramp voltage exceeds the internal reference of 0.6 V.
ENx
1
CONTROL ARCHITECTURE
The ADP2114 consists of two step-down, dc-to-dc converters that deliver regulated output voltages, VOUT1 and VOUT2 (see Figure 1), by modulating the duty cycle at which the internal high-side, P-channel power MOSFET and the low-side, N-channel power MOSFET are switched on and off. In steady-state operation, the output voltage, VOUT, is sensed on the feedback pin, FB1 (FB2), and attenuated in proportion to the selected output voltage on the V1SET (V2SET) pin. An error amplifier integrates the error between the feedback voltage and the reference voltage (VREF = 0.6 V) to generate an error voltage at the COMP1 (COMP2) pin. The valley inductor current is sensed by a current-sense amplifier when the low-side, N-channel MOSFET is on. An internal oscillator turns off the low-side, N-channel MOSFET and turns on the high-side, P-channel MOSFET at a fixed switching frequency. When the high,-side P-channel MOSFET is enabled, the valley inductor current information is added to an emulated ramp signal and compared to the error voltage by the PWM comparator. The output of the PWM comparator modulates the duty cycle by adjusting the trailing edge of the PWM pulse that switches the power devices. Slope compensation is programmed internally into the emulated ramp signal and automatically selected, depending on the VIN, VOUT, and switching frequency. This prevents subharmonic oscillations on the inductor current for greater than 50% duty-cycle operation. Control logic with the antishoot-through circuit monitor and adjust the low-side and high-side driver outputs to ensure breakbefore-make switching. This monitoring and control prevents crossconduction between the internal high-side, P-channel power MOSFET and the low-side, N-channel power MOSFET.
VOUT
2
4
SSx
SW
3
08143-066
CH1 5.0V CH3 5.0V
CH2 1.0V CH4 2.0V
M1.0ms
A CH1
2.4V
Figure 66. Soft Start
Rev. 0 | Page 21 of 40
ADP2114
The capacitance value of the soft start capacitor defines the soft start time, tSS, based on The power good thresholds are shown in Figure 68. The PGOOD1 and PGOOD2 outputs also sink current if an overtemperature condition is detected. Use these outputs as logical power good signals by connecting the pull-up resistors from PGOOD1 (PGOOD2) to VDD. If the power good function is not used, the pins can be left floating.
VOUT RISING 116% VOUT FALLING
VREF I SS = t SS CSS
where: VREF is the internal reference voltage, 0.6 V. ISS is the soft start current, 6 A. CSS is the soft start capacitor value.
(1)
% OF VOUT SET
If the output voltage VOUT1 (VOUT2) is precharged prior to enabling Channel 1 (Channel 2), the control logic prevents inductor current reversal by holding the power MOSFETs off until the soft start voltage ramp at SS1 (SS2) reaches the precharged output voltage on VFB1 (VFB2), see Figure 67.
108% 100% 92% 84% 100%
UNDERVOLTAGE
POWER GOOD PGOOD1 (PGOOD2)
OVERVOLTAGE
POWER GOOD
UNDERVOLTAGE
08143-068
ENx
1
VOUT
2
Figure 68. PGOOD1 and PGOOD2 Thresholds
PULSE SKIP MODE
SSx
4
SW
3
08143-067
CH1 5.0V CH3 5.0V
CH2 1.0V CH4 500mV
M200s
A CH1
2.4V
Figure 67. Start with a Precharged Load
POWER GOOD
The ADP2114 features open-drain, power-good outputs (PGOOD1 and PGOOD2) that indicate when the converter output voltage is within regulation. The power good signal transitions low immediately when the corresponding channel is disabled. The power good circuitry monitors the output voltage on the FB1 (FB2) pin and compares it to the rising and falling thresholds shown in Table 1. If the output voltage, VOUT1 (VOUT2), exceeds the typical rising limit of 116% of the target output voltage, VOUT1SET (VOUT2SET), the PGOOD1 (PGOOD2) pin pulls low. The PGOOD1 (PGOOD2) pin continues to pull low until the output voltage recovers down to 108% (typical) of the target value. If the output voltage drops below 84% of the target output voltage, the corresponding PGOOD1 (PGOOD2) pin pulls low. The PGOOD1 (PGOOD2) pin continues to pull low until the output voltage rises to within 92% of the target output voltage. The PGOOD1 (PGOOD2) pin then releases and signals the return of the output voltage within the power good window.
The ADP2114 has built-in, pulse skip circuitry that turns on during light loads, switching only as necessary to maintain the output voltage within regulation. This allows the converter to maintain high efficiency during light load operation by reducing the switching losses. The pulse skip mode can be selected by configuring the OPCFG pin according to Table 7. In pulse skip mode, when the output voltage dips below regulation, the ADP2114 enters PWM mode for a few oscillator cycles to increase the output voltage back to regulation. During the wait time between bursts, both power switches are off, and the output capacitor supplies all load current. Because the output voltage dips and recovers occasionally, the output voltage ripple in this mode is larger than the ripple in the PWM mode of operation. If the converter is configured to operate in forced PWM mode (by selecting that configuration on the OPCFG pin), the device operates with a fixed switching frequency, even at light loads.
Rev. 0 | Page 22 of 40
% OF VOUT SET
ADP2114
HICCUP MODE CURRENT LIMIT
The ADP2114 features a hiccup mode current limit implementation. When the peak inductor current exceeds the preset current limit for more than eight consecutive clock cycles, the hiccup mode current limit condition occurs. The channel then goes to sleep for 6.8 ms (at a 600 kHz switching frequency), which is enough time for the output to discharge and the average power dissipation to reduce. It then wakes up with a soft start period (see Figure 69). If the current limit condition is triggered again, the channel goes to sleep and wakes up after 6.8 ms. The current limits for the two channels are programmed by configuring the OPCFG pin (see Table 7). For the 2 A/2 A option, the output current limit is set to 3.3 A per output. For the 3 A/1 A option, the current limits are set to 4.5 A and 1.9 A for VOUT1 and VOUT2, respectively.
MAXIMUM DUTY CYCLE OPERATION
As the input voltage drops and approaches the output voltage, the ADP2114 smoothly transitions to maximum duty cycle operation, maintaining the low-side, N-channel MOSFET switch on for the minimum off time. In maximum duty cycle operation, the output voltage dips below regulation because the output voltage is the product of the input voltage and the maximum duty cycle limitation. The maximum duty cycle limit is a function of the switching frequency and the input voltage, as shown in Figure 72.
SYNCHRONIZATION
The ADP2114 can be synchronized to an external clock such that the two channels operate at a switching frequency that is half the input synchronization clock. The SYNC/CLKOUT pin can be configured as an input SYNC pin or an output CLKOUT pin through the SCFG pin, as shown in Table 6. Through the input SYNC pin, the ADP2114 can be synchronized to an external clock such that the two channels switch at half the external clock, 180 out of phase. Through the output CLKOUT pin, the ADP2114 provides an output clock that is twice the switching frequency of the channels and 90 out of phase. Therefore, a single ADP2114 configured for the CLKOUT option acts as the master converter and provides an external clock for all other dc-to-dc converters (including other ADP2114s). These other converters are configured as slaves that accept an external clock and synchronize to it. This clock distribution approach synchronizes all dc-to-dc converters in the system and prevents beat harmonics that can lead to EMI issues. The ADP2114 has been optimized to power high performance signal chain circuits. The slew rate of the switch node is controlled by the size of the driver devices. Fast slewing of the switch node is desirable to minimize transition losses but can lead to serious EMI issues due to parasitic inductance. Therefore, the slew rate of the drivers has been optimized such that the ADP2114 can match the performance of the low dropout regulators in supplying sensitive signal chain circuits while providing excellent power efficiency.
INDUCTOR CURRENT
4
VOUT
2
SW
3
CH3 5.0V
CH2 1.0V CH4 2A
M2.0ms
A CH4
1.72A
Figure 69. Hiccup Mode
THERMAL OVERLOAD PROTECTION
The ADP2114 has an internal temperature sensor that monitors the junction temperature. High current going into the switches or a hot printed circuit board (PCB) can cause the junction temperature of the ADP2114 to rise rapidly. When the junction temperature reaches approximately 150C, the ADP2114 goes into thermal shutdown and the converter is turned off. When the junction temperature drops below 125C, the ADP2114 resumes normal operation after the soft start sequence.
08143-069
Rev. 0 | Page 23 of 40
ADP2114 CONVERTER CONFIGURATION
SELECTING THE OUTPUT VOLTAGE
To set the output voltage, VOUT1 (VOUT2), select one of the six fixed voltages, as shown in Table 4, by connecting the V1SET (V2SET) pin to GND through an appropriate value resistor (see Figure 70). V1SET and V2SET set the voltage output levels for Channel 1 and Channel 2, respectively. The feedback pin FB1 (FB2) should be directly connected to VOUT1 (VOUT2). Table 4. Output Voltage Programming
RV1SET () 5% 0 to GND 4.7 k to GND 8.2 k to GND 15 k to GND 27 k to GND 47 k to GND 82 k to GND 0 to VDD VOUT1 (V) 0.8 1.2 1.5 1.8 2.5 3.3 0.6 to <1.6 (adjustable) 1.6 to 3.3 (adjustable) RV2SET () 5% 0 to GND 4.7 k to GND 8.2 k to GND 15 k to GND 27 k to GND 47 k to GND 82 k to GND 0 to VDD VOUT2 (V) 0.8 1.2 1.5 1.8 2.5 3.3 0.6 to <1.6 (adjustable) 1.6 to 3.3 (adjustable)
To limit output voltage accuracy degradation due to FB bias current to less than 0.05% (0.5% maximum), ensure that the divider string current is greater than 20 A. To calculate the desired resistor values, first determine the value of the bottom divider string resistor, R1, by R1 = VREF/ISTRING where: VREF is 0.6 V, the internal reference. ISTRING is the resistor divider string current. When R1 is determined, calculate the value of the top resistor, R2, by
V - VREF R2 = R1 OUT VREF
VIN RFREQ RV1SET / RV2SET
(2)
(3)
VDD FREQ
V1SET/ V2SET VINx
ADP2114
SWx FB1/FB2 PGNDx COMP1/ COMP2 L
VOUT1/VOUT2
If the required output voltage VOUT1 (VOUT2) is in the adjustable range, from 0.6 V to less than 1.6 V, connect V1SET (V2SET) through an 82 k resistor to GND. For the adjustable output voltage range of 1.6 V to 3.3 V, tie V1SET (V2SET) to VDD (see Table 4). The adjustable output voltage of ADP2114 is externally set by a resistive voltage divider from the output voltage to the feedback pin (see Figure 71). The ratio of the resistive voltage divider sets the output voltage, while the absolute value of those resistors sets the divider string current. For lower divider string currents, the small 10 nA (0.1 A maximum) FB bias current should be taken into account when calculating the resistor values. The FB bias current can be ignored for a higher divider string current; however, this degrades efficiency at very light loads.
Figure 70. Configuration for Fixed Outputs
VIN RFREQ RV1SET / RV2SET
VDD FREQ
V1SET/ V2SET VINx
ADP2114
SWx FB1/FB2 PGNDx GND COMP1/ COMP2
L R2 R1
VOUT1/VOUT2
08143-070 08143-071
GND
Figure 71. Configuration for Adjustable Outputs
Rev. 0 | Page 24 of 40
ADP2114
SETTING THE OSCILLATOR FREQUENCY
The ADP2114 channels can be set to operate in one of the three preset switching frequencies: 300 kHz, 600 kHz, or 1.2 MHz. For 300 kHz operation, connect the FREQ pin to GND. For 600 kHz or 1.2 MHz operation, connect a resistor between the FREQ pin and GND, as shown in Table 5. Table 5. Oscillator Frequency Setting
RFREQ () 5% 0 to GND 8.2 k to GND 27 k to GND fSW (kHz) 300 600 1200
SCFG FREQ VDD SCFG FREQ VDD SYNC (fSW = fSYNC /2) SYNC (fSW = fSYNC /2)
An external clock can be applied to the SYNC/CLKOUT pin when configured as an input to synchronize multiple ADP2114s to the same external clock. The fSYNC range is 400 kHz to 4 MHz, which produces fSW in the 200 kHz to 2 MHz range. See Figure 73 for an illustration.
VIN 27k 27k
Choice of the switching frequency depends on the required dc-to-dc conversion ratio and is limited by the minimum and maximum controllable duty cycle shown on Figure 72. This is due to the requirement of minimum on and minimum off times for current sensing and robust operation. The choice of switching frequency is also determined by the need for small external components. For small, area limited power solutions, use of higher switching frequencies is recommended.
100 90 80
DUTY-CYCLE LIMITS (%)
EXTERNAL CLOCK (2.4MHz)
TO OTHER ADP2114
Figure 73. Synchronization with External Clock (fSW = 1.2 MHz in This Case)
When synchronizing to an external clock, the switching frequency fSW must be set close to half of the expected external clock frequency by appropriately terminating the FREQ pin as shown in Table 5.
VIN 8.2k 8.2k
SCFG
FREQ
VDD
SCFG
FREQ
VDD
70 60 50 40 30 20 10 400 600 800 1000 1200
08143-072
SYNC (fSW = fSYNC /2)
CLKOUT (fSW = 2 x fSW)
ADP2114
MAXIMUM LIMIT MINIMUM LIMIT; VIN = 2.75V MINIMUM LIMIT; VIN = 3.3V MINIMUM LIMIT; VIN = 5.5V
ADP2114
fSYNC = 2 x fSW
TO OTHER ADP2114 NOTES 1. fSW = 600kHz SET FOR BOTH ADP2114.
08143-074
Figure 74. ADP2114 to SYNC with Another ADP2114 (Note that the SCFG of the master is tied to VDD.)
0 200
SWITCHING FREQUENCY (kHz)
Figure 72. Duty Cycle Working Limits
For single output, multiphase applications that operate at close to 50% duty cycle, it is recommended to use the 1.2 MHz switching frequency to minimize crosstalk between the phases.
The ADP2114 can also be configured to output a clock signal on the SYNC/CLKOUT pin to synchronize multiple ADP2114s to it (see Figure 74). The CLKOUT signal is 90 phase shifted to the internal clock of the channels so that the master ADP2114 and the slave channels are out of phase (see Figure 75 for additional information).
CHANNEL 1 SW
SYNCHRONIZATION AND CLKOUT
The ADP2114 can be configured to output an internal clock or synchronize to an external clock at the STNC/CLKOUT pin. The SYNC/CLKOUT pin is a bidirectional pin configured by the SCFG pin, as shown in Table 6. Table 6. SYNC/CLKOUT Configuration Setting
SCFG GND VDD SYNC/CLKOUT Input Output
1 4
CHANNEL 2 SW
3
INTERNAL CLKOUT CH1 5.0V CH3 5.0V M1.0s CH4 5.0V A CH4 3.00V
08143-075
The converter switching frequency, fSW, is half of the synchronization frequency fSYNC/fCLKOUT as shown in Equation 4, irrespective of whether SYNC/CLKOUT is configured as an input or output. fSYNC/fCLKOUT = 2 x fSW (4)
Rev. 0 | Page 25 of 40
Figure 75. CLKOUT Waveforms
08143-073
fSYNC
ADP2114
ADP2114
ADP2114
OPERATION MODE CONFIGURATION
The dual-channel ADP2114 can be configured to one of the four modes of operation by connecting the OPCFG pin as shown in Table 7. This configuration sets the current limit for each channel and enables or disables the transition to pulse skip mode at light loads. In the dual-phase configuration, the outputs of the two channels are connected together, and they generate a single dc output voltage, VOUT. For this single combined dual-phase output, only Mode 2 in the OPCFG options can be used. In this mode, the error amplifiers of both phases are used. The feedback pins (FB1 and FB2) are tied together, the compensation pins (COMP1 and COMP2) are tied together, the soft start pins (SS1 and SS2) are tied together, and the enable pins (EN1 and EN2) are tied together. In addition, if the power-good feature is used, combine PGOOD1 and PGOOD2 and connect them to VDD through a single pull-up resistor. When the ADP2114 is synchronized to an external clock, the converters always operate in fixed frequency CCM, and they do not enter into pulse skip mode at light loads. In this case, when configuring the OPCFG pin, choose forced PWM mode.
Table 7. Current Limit Operation Mode and Configuration
Mode 1 2 3 4 ROPCFG () 5% 0 to GND 4.7 k to GND 8.2 k to GND 15 k to GND Maximum Output Current IOUT1 (A)/IOUT2 (A) 2/2 2/2 3/1 3/1 Peak Current Limit ILIMIT1 (A)/ILIMIT2 (A) 3.3/3.3 3.3/3.3 4.5/1.9 4.5/1.9 Power Savings at Light Load Pulse skip enabled Forced PWM Pulse skip enabled Forced PWM
Rev. 0 | Page 26 of 40
ADP2114 EXTERNAL COMPONENTS SELECTION
INPUT CAPACITOR SELECTION
The input current to a buck converter is pulsating in nature. The current is zero when the high-side switch is off and approximately equal to the load current when it is on. Because this occurs at reasonably high frequencies (300 kHz to 1.2 MHz), the input bypass capacitor ends up supplying most of the high frequency current (ripple current), allowing the input power source to supply only the average (dc) current. The input capacitor needs a sufficient ripple current rating to handle the input ripple as well as an ESR that is low enough to mitigate the input voltage ripple. For the ADP2114, place a 22 F, 6.3 V, X5R ceramic capacitor close to the VINx pin for each channel. X5R or X7R dielectrics are recommended with a voltage rating of 6.3 V or 10 V. Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics. The internal slope compensation introduces additional limitations on the optimal inductor value for stable operation because the internal ramp is scaled for each VOUT setting. The limits for different VIN, VOUT, and fSW combinations are listed in Table 8. Table 8. Minimum and Maximum Inductor Values
fSW (kHz) 300 300 300 300 300 300 300 300 300 300 300 600 600 600 600 600 600 600 600 600 600 600 1200 1200 1200 1200 1200 1200 1200 1200 1200 VIN (V) 5 5 3.3 5 3.3 5 3.3 5 3.3 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3 VOUT (V) 3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 1.2 0.8 0.8 3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 1.2 0.8 0.8 2.5 1.8 1.8 1.5 1.5 1.2 1.2 0.8 0.8 Min L (H) 6.8 5.6 5.6 4.7 4.7 2.2 2.2 2.2 2.2 1.5 1.5 3.3 3.3 3.3 2.2 2.2 1.5 1.5 1.5 1.5 1.0 1.0 1.0 1.0 1.0 0.8 0.8 0.8 0.8 0.47 0.47 Max L (H) 10 15 6.8 12 8.2 12 8.2 10 8.2 6.8 6.8 4.7 6.8 3.3 6.8 3.3 5.6 4.7 4.7 3.3 3.3 3.3 3.3 3.3 2.2 2.2 2.2 2.2 2.2 1.5 1.5
VDD RC FILTER
It is recommended to apply the input power, VIN, to the VDD pin through a low-pass RC filter, as shown on Figure 76. Connecting a 10 resistor in series with VIN and a 1 F, 6.3 V, X5R (or X7R) ceramic capacitor between VDD and GND creates a 16 kHz (-3 dB) low-pass filter that effectively attenuates voltage glitches on the input power rail caused by the switching regulator. This provides a clean power supply to the internal, sensitive, analog and digital circuits in the ADP2114, ensuring robust operation.
VIN 10 1F VDD
ADP2114
08143-076
GND
Figure 76. Low-Pass Filter at VDD
INDUCTOR SELECTION
The high switching frequency of ADP2114 allows for minimal output voltage ripple even with small inductors. The sizing of the inductor is a trade-off between efficiency and transient response. A small inductor leads to larger inductor current ripple that provides excellent transient response but degrades efficiency. Due to the high switching frequency of ADP2114, shielded ferrite core inductors are recommended for their low core losses and low EMI. As a guideline, the inductor peak-to-peak current ripple, IL, is typically set to 1/3 of the maximum load current for optimal transient response and efficiency.
I L = VOUT x (VIN - VOUT ) I LOAD (MAX ) VIN x f SW x L 3
3 x VOUT x (VIN - VOUT ) f SW x VIN x I LOAD ( MAX )
To avoid saturation, the rated current of the inductor has to be larger than the maximum peak inductor IL_PEAK current given by
I L _ PEAK = I LOAD _ MAX +
I L 2
(6)
where: ILOAD_MAX is the maximum dc load current. IL is the inductor ripple current (peak to peak).
(5)
LIDEAL =
where: VIN is the input voltage on the VINx terminal. VOUT is the desired output voltage. fSW is the converter switching frequency.
Rev. 0 | Page 27 of 40
ADP2114
The ADP2114 can be configured in either a 2 A/2 A or a 3 A/1 A current limit configuration and, therefore, the current limit thresholds for the two channels are different in each setting. The inductor chosen for each channel must have at least the peak output current limit of the IC in each case for robust operation during short-circuit conditions. The following inductors are recommended: * * From 0.47 H to 4.7 H, the TOKO D53LC and FDV0620 series From 4.7 H to 12 H, the Cooper Bussman DR1050 series and the Wurth Elektronik WE-PDF series.
Note that the previous equations are approximations and are based on following assumptions:
* * *
The inductor value is based on the peak-to-peak current being 30% of the maximum load current. Voltage drops across the internal MOSFET switches and across the dc resistance of the inductor are ignored. In Equation 9, it is assumed that it takes up to three switching cycles until the loop adjusts the inductor current in response to the load step.
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. The ADP2114 is designed for operation with small ceramic output capacitors that have low ESR and ESL; therefore, comfortably able to meet tight output voltage ripple specifications. X5R or X7R dielectrics are recommended with a voltage rating of 6.3 V or 10 V. Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics. The minimum output capacitance, COUT_MIN, is determined by Equation 7 and Equation 8. For acceptable maximum output voltage ripple,
1 VRIPPLE I L x ESR + 8 x f SW x COUT_MIN
Select the largest output capacitance given by Equation 8 and Equation 9. While choosing the actual type of ceramic capacitor for the output filter of the converter, pick one with a nominal capacitance that is 20% to 30% larger than the calculated value because the effective capacitance decreases with larger dc voltages. In addition, the rated voltage of the capacitor must be higher than the output voltage of the converter. Recommended input and output ceramic capacitors include
* * * *
Murata GRM21BR61A106KE19L, 10 F, 10 V, X5R, 0805 TDK C2012X5R0J226M, 22 F, 6.3 V, X5R, 0805 Panasonic ECJ-4YB0J476M, 47 F, 6.3 V, X5R, 1210 Murata GRM32ER60J107ME20L, 100 F, 6.3 V, X5R, 1210
CONTROL LOOP COMPENSATION
(7)
Therefore,
COUT_MIN I L 8 x f SW x (VRIPPLE -- I L x ESR)
The ADP2114 uses a peak, current mode control architecture for excellent load and line transient response. The external voltage loop is compensated by a transconductance amplifier with a simple external RC network between the COMP1 (COMP2) pin and GND, as shown in Figure 77.
ADP2114
VFBx COMPx RCOMP CCOMP 0.6V GND CC2
(8)
If there is a step load, choose the output capacitor value based on the value of the step load. For the maximum acceptable output voltage droop/overshoot caused by the step load,
Figure 77. Compensation Components
The basic control loop block diagram is shown in Figure 78.
VIN INDUCTOR CURRENT SENSE PULSE WIDTH MODULATOR IL VOUT
COUT_MIN
3 I OUT_STEP x f x V DROOP SW

(9)
where: IOUT_STEP is the load step value in amperes. fSW is the switching frequency in Hertz. VDROP is the maximum allowable output voltage droop/overshoot in volts for the load step.
VCOMP CCOMP RCOMP
gm
VREF = 0.6V
08143-078
ADP2114
Figure 78. Basic Control Block Diagram
The blocks and components shown enclosed within the dashed line in Figure 78 are embedded inside each channel of the ADP2114.
Rev. 0 | Page 28 of 40
08143-077
where: VRIPPLE is allowable peak-to-peak output voltage ripple in volts. IL is the inductor ripple current. ESR is the equivalent series resistance of the capacitor in ohms. fSW is the converter switching frequency in Hertz.
gm
ADP2114
The control loop can be broken down into the following three sections:
* VOUT to VCOMP * VCOMP to IL * IL to VOUT Correspondingly, there are three transfer functions:
VCOMP(s) VREF = x g m x ZCOMP(s) VOUT (s) VOUT (10) (11) (12)
At the crossover frequency, the gain of the open-loop transfer function is unity. This yields Equation 16 for the compensation network impedance at the crossover frequency.
ZCOMP ( fCROSS ) =
2 x x fCROSS x COUT VOUT x g m x GCS VREF
(16)
To ensure that there is sufficient phase margin at the crossover frequency, place the compensator zero at 1/8 of the crossover frequency, as shown in Equation 17.
f ZERO = f 1 CROSS 2 x x RCOMP x CCOMP 8
I L(s) = GCS VCOMP(s)
VOUT (s) = Z FILT (s) I L(s)
(17)
Solving Equation 16 and Equation 17 simultaneously yields the value for the compensation resistor and compensation capacitor, as shown in Equation 18 and Equation 19.
(2 )FCROSS RCOMP = 0.9 x GG m CS COUT VOUT x V REF
where: gm is the transconductance of the error amplifier, 550 s. GCS is the current sense gain, 4 A/V. VOUT is the output voltage of the converter. VREF is the internal reference voltage of 0.6 V. ZCOMP(s) is the impedance of the RC compensation network that forms a pole at origin and a zero as expressed in Equation 13.
(18)
CCOMP =
1 2 x x f ZERO x RCOMP
(19)
ZCOMP(s) =
1 + s x RCOMP x CCOMP s x CCOMP
(13)
ZFILT(s) is the impedance of the output filter and is expressed as ZFILT(s) = RLOAD 1 + s x RLOAD x COUT
The capacitor CC2 (as shown in Figure 77) forms a pole with the compensation resistor, RCOMP, in the feedback loop to ensure that the loop gain keeps rolling off well beyond the unity-gain crossover frequency. The value of CC2, if used, is typically set to 1/40 of the compensation capacitor, CCOMP.
(14)
where s is angular frequency that can be written as s = 2f. The overall loop gain, H(s), is obtained by multiplying the three transfer functions previously mentioned as follows:
H(s) = gM x GCS x VREF x ZCOMP(s) x ZFILT(s) VOUT
(15)
When the switching frequency (fSW), output voltage (VOUT), output inductor (L), and output capacitor (COUT) values are selected, the unity crossover frequency of 1/12 (approximately) the switching frequency can be targeted.
Rev. 0 | Page 29 of 40
ADP2114 DESIGN EXAMPLE
The external component selection procedure from the Control Loop Compensation section is used for this design example.
Table 9. 2-Channel Step-Down DC-to-DC Converter Requirements
Parameter Input Voltage, VIN Channel 1, VOUT1 Specification 5.0 V 10% 3.3 V, 2 A, 1% VOUT ripple (p-p) 1.8 V, 2 A, 1% VOUT ripple (p-p) Enabled Additional Requirements None Maximum load step: 1 A to 2 A, 5% droop maximum Maximum load step: 1 A to 2 A, 5% droop maximum None
3.
Select the inductor by using Equation 5.
L= (VIN - VOUT ) VOUT x VIN I L x f SW
In Equation 5, VIN = 5 V, VOUT = 3.3 V, IL = 0.3 x IL = 0.6 A, and fSW = 600 kHz, which results in L = 3.11 H. Therefore, when L = 3.3 H (the closest standard value) in Equation 3, IL = 0.566 A. Although the maximum output current required is 2 A, the maximum peak current is 3.3 A under the current limit condition (see Table 7). Therefore, the inductor should be rated for 3.3 A of peak current and 3 A of average current for reliable circuit operation. 4. Select the output capacitor by using Equation 8 and Equation 9.
COUT_MIN I L 8 x f SW x (VRIPPLE - I L x ESR)
Channel 2, VOUT2
Pulse-Skip Feature
CHANNEL 1 CONFIGURATION AND COMPONENTS SELECTION
Complete the following steps to configure Channel 1: 1. For the target output voltage, VOUT = 3.3 V, connect the V1SET pin through a 47 k resistor to GND (see Table 4). Because one of the fixed output voltage options is chosen, the feedback pin (FB1) must be directly connected to the output of Channel 1, VOUT1. Estimate the duty-cycle, D, range. Ideally,
D= VOUT V IN
3 COUT_MIN IOUT_STEP x f x V DROOP SW

2.
(20)
Equation 8 is based on the output ripple (VRIPPLE), and Equation 9 is for capacitor selection based on the transient load performance requirements that allow, in this case, 5% maximum deviation. As previously mentioned, perform these calculations and choose whatever equation yields the larger capacitor size. In this case, the following values are substituted for the variables in Equation 8 and Equation 9: IL = 0.566 A fSW = 600 kHz VRIPPLE = 33 mV (1% of 3.3 V) ESR = 3 m (typical for ceramic capacitors) IOUT_STEP = 1 A VDROOP = 0.165 V (5% of 3.3 V) The output ripple based calculation (see Equation 8) dictates that COUT = 4.0 F, whereas the transient load based calculation (see Equation 9) dictates that COUT = 30 F. To meet both requirements, choose the latter. As previously mentioned in the Control Loop Compensation section, the capacitor value reduces with applied dc bias; therefore, select a higher value. In this case, the next higher value is 47 F with a minimum voltage rating of 6.3 V. 5. Calculate the feedback loop, compensation component values by using Equation 15.
H(s) = gM x GCS x VREF x ZCOMP(s) x ZFILT(s) VOUT
That gives the duty cycle for the 3.3 V output voltage and the nominal input voltage of DNOM = 0.66 at VIN = 5.0 V. The minimum duty cycle, DMIN, for the maximum input voltage (10% above the nominal) is DMIN = 0.60 at VIN maximum = 5.5 V The maximum duty cycle, DMAX, for the minimum input voltage (10% less than nominal) is DMAX = 0.73 at VIN minimum = 4.5 V. However, the actual duty cycle is larger than the calculated values to compensate for the power losses in the converter. Therefore, add 5% to 7% at the maximum load. Based on the estimated duty-cycle range, choose the switching frequency according to the minimum and maximum duty-cycle limitations, as shown in Figure 72. For the Channel 1 VIN = 5 V and VOUT = 3.3 V combination, choose fSW = 600 kHz with a maximum duty cycle of 0.8. This frequency option provides the smallest sized solution. If a higher efficiency is required, choose the 300 kHz option. However, the PCB footprint area of the converter will be larger because of the bigger inductor and output capacitors.
Rev. 0 | Page 30 of 40
ADP2114
In this case, the following values are substituted for the variables in Equation 18: gm = 550 s GCS = 4A/V VREF = 0.6 V VOUT = 3.3 V COUT = 0.8 x 47 F (capacitance derated by 20% to account for dc bias). From Equation 18, RCOMP = 27 k. Substituting RCOMP in Equation 19 yields CCOMP = 1000 pF.
Table 10. Channel 1 Circuit Settings
Circuit Parameter Output Voltage, VOUT Reference Voltage, VREF Error Amp Transconductance, gm Current Sense Gain, CCS Switching Frequency, fSW Crossover Frequency, fC Zero Frequency, fZERO Output Inductor, LOUT Output Capacitor, COUT Compensation Resistor, RCOMP Compensation Capacitor, CCOMP Setting Step 1 Fixed, typical Fixed, typical Fixed, typical Step 2 1/12 fSW 1/8 fCROSS Step 3 Step 4 Equation 18 Equation 19 Value 3.3 V 0.6 V 550 s 4 A/V 600 kHz 50 kHz 6.25 kHz 3.3 H 47 F, 6.3 V 27 k 1000 pF
The switching frequency (fSW) of 600 kHz, which is chosen based on the Channel 1 requirements, meets the duty cycle ranges that have been previously calculated. Therefore, this switching frequency is acceptable. 3. Select the inductor by using Equation 5.
L= (VIN - VOUT ) VOUT x I L x f SW VIN
In Equation 5, VIN = 5 V, VOUT = 1.8 V, IL = 0.3 x IL = 0.6 A, and fSW = 600 kHz, which results in L = 2.9 H. Therefore, when L = 3.3 H (the closest standard value) in Equation 3, IL = 0.582 A. Although the maximum output current required is 2 A, the maximum peak current is 3.3 A under the current limit condition (see Table 7). Therefore, the inductor should be rated for 3.3 A of peak current and 3 A of average current for reliable circuit operation under all conditions. 4. Select the output capacitor by using Equation 8 and Equation 9.
COUT_MIN I L 8 x f SW x (VRIPPLE - I L x ESR)
3 COUT_MIN I OUT_STEP x f x V DROOP SW

CHANNEL 2 CONFIGURATION AND COMPONENTS SELECTION
Complete the following steps to configure Channel 2: 1. For the target output voltage, VOUT = 1.8 V, connect the V2SET pin through a 15 k resistor to GND (see Table 4). Because one of the fixed output voltage options is chosen, the feedback pin (FB2) must be directly connected to the output of Channel 2, VOUT2. Estimate the duty-cycle, D, range (see Equation 20). Ideally,
D= VOUT V IN
2.
That gives the duty cycle for the 1.8 V output voltage and the nominal input voltage of DNOM = 0.36 at VIN = 5.0 V. The minimum duty cycle for the maximum input voltage (10% above the nominal) is DMIN = 0.33 at VIN maximum = 5.5 V. The maximum duty cycle for the minimum input voltage (10% less than nominal) is DMAX = 0.4 at VIN minimum = 4.5 V. However, the actual duty cycle is larger than the calculated values to compensate for the power losses in the converter. Therefore, add 5% to 7% at the maximum load.
Equation 8 is based on the output ripple (VRIPPLE), and Equation 9 is for capacitor selection based on the transient load performance requirements that allow, in this case, 5% maximum deviation. As mentioned earlier, perform these calculations and choose whatever equation yields the larger capacitor size. In this case, the following values are substituted for the variables in Equation 8 and Equation 9: IL = 0.582 A fSW = 600 kHz VRIPPLE = 18 mV (1% of 1.8 V) ESR = 3 m (typical for ceramic capacitors) IOUT_STEP = 1 A VDROOP = 0.09 V (5% of 1.8 V) The output ripple based calculation (see Equation 8) dictates that COUT = 7.7 F, whereas the transient load based calculation (see Equation 9) dictates that COUT = 55 F. To meet both requirements, choose the latter. As previously mentioned in the Control Loop Compensation section, the capacitor value reduces with applied dc bias; therefore, select a higher value. In this case, choose a 47 F/6.3 V capacitor and a 22 F/6.3 V capacitor in parallel to meet the requirements.
Rev. 0 | Page 31 of 40
ADP2114
5. Calculate the feedback loop, compensation component values by using Equation 15.
V H(s) = gm x GCS x REF x ZCOMP(s) x ZFILT(s) VOUT
SYSTEM CONFIGURATION
Complete the following steps to further configure the ADP2114 for this design example: 1. Set the switching frequency (fSW) = 600 kHz (see Table 5) by connecting the FREQ pin through an 8.2 k resistor to GND. Tie SCFG to VDD and use the CLKOUT signal to synchronize other converters on the same board with the ADP2114. Tie OPCFG to GND for 2 A/2 A maximum output current operation and to enable pulse skip mode at light load conditions (see Table 7).
In this case, the following values are substituted for the variables in Equation 18: gm = 550 s GCS = 4 VREF = 0.6 V VOUT = 1.8 V COUT = 0.8 x (47+22) F (capacitance derated by 20% to account for dc bias). From Equation 18, RCOMP = 22 k. Substituting RCOMP in Equation 19 yields CCOMP = 1100 pF.
Table 11. Channel 2 Circuit Settings
Circuit Parameter Output Voltage, VOUT Reference Voltage, VREF Error Amp Transconductance, gm Current Sense Gain, CCS Switching Frequency, fSW Crossover Frequency, fCROSS Zero Frequency, fZERO Output Inductor, LOUT Output Capacitors, COUT Compensation Resistor, RCOMP Compensation Capacitor, CCOMP Setting Nominal Typical Typical Typical Step 2 1/12 fSW 1/8 fCROSS Step 3 Step 4 Equation 18 Equation 19 Value 1.8 V 0.6 V 550 s 4 A/V 600 kHz 50 kHz 6.25 kHz 3.3 F 47 F + 22 F 22 k 1100 pF
2.
3.
A schematic of the ADP2114 as configured in the design example described in this section is shown in Figure 79. Table 12 provides the recommended inductor, output capacitor, and compensation component values for a set of popular input and output voltage combinations.
Table 12. Selection Table of L, COUT, and Compensation Values
fSW (kHz) 300 300 300 300 600 600 600 600 1200 1200 1200 1200 VIN (V) 5 5 5 5 5 5 5 5 5 5 5 5 VOUT (V) 3.3 2.5 1.8 1.2 3.3 2.5 1.8 1.2 2.5 1.8 1.2 0.8 Maximum Load (A) 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 L (H) 6.8 6.8 6.8 4.7 3.3 3.3 3.3 2.2 1.8 1.8 1.2 1.0 COUT (F) 69 (47 + 22) 100 147 (100 + 47) 200 (2 x 100 ) 47 57 (47 + 10) 69 (47 + 22) 100 32 (22 + 10) 44 (2 x 22) 57 (47 + 10) 100 RCOMP (k) 20 22 22 20 27 24 22 20 27 27 24 27 CCOMP (pF) 2400 2400 2400 2400 1000 1100 1100 1200 470 470 510 470
Rev. 0 | Page 32 of 40
ADP2114 APPLICATION CIRCUITS
VIN = 5V 10 100k 1F 100k EN1 VIN1 VIN2 VIN3 PGOOD1 SW1 SW2 47F
22F PGOOD2 VOUT2 = 1.8V, 2A 22F 47F 3.3H
VIN4 VIN5 VIN6 PGOOD2 SW3 SW4 PGND3 PGND4 FB2 V2SET
VDD
EN2
22F PGOOD1 3.3H VOUT1 = 3.3V, 2A
ADP2114
PGND1 PGND2 FB1 V1SET 47k
SYNC
15k
SYNC/CLKOUT COMP2 SS2 10nF
FREQ OPCFG SCFG GND
22k 1100pF
COMP1 SS1
10nF
27k 1000pF
08143-079
8.2k
fSW = 600kHz
Figure 79. Application Circuit for 2 A/2 A Outputs
VIN = 5V
100k
10 10F 4.7k 1F
10F
SCFG
VDD
PGOOD2 V2SET VIN4 VIN5 VIN6
PGOOD1 V1SET VIN1 VIN2 VIN3
4.7k
PGOOD
1.2H 47F
SW3 SW4 FB2
ADP2114
SW1 SW2 FB1
1.2H 47F
VOUT = 1.2V, 4A 22F
PGND1 PGND2 COMP1 12k
PGND3 PGND4 COMP2 SYNC/CLKOUT
OPCFG GND
VIN
27k 4.7k
Figure 80. Application Circuit for a Single 4 A Output
Rev. 0 | Page 33 of 40
08143-080
22nF
FREQ
1000pF
SS1 SS2 EN1 EN2
fSW = 1.2MHz
ADP2114
VIN = 5V 10 100k 1F 100k
22F PGOOD2 VOUT2 = 3.3V, 1A 6.8H
VIN4 VIN5 VIN6 PGOOD2 SW3 SW4
SCFG
VDD
EN2
EN1 VIN1 VIN2
22F PGOOD1 6.8H VOUT1 = 1.8V, 3A 47F 100F
VIN3 PGOOD1 SW1 SW2
ADP2114
22F
47F
PGND3 PGND4 FB2 V2SET SYNC/CLKOUT
PGND1 PGND2 FB1 V1SET 15k
CLKOUT
47k
OPCFG
GND
20k 2.4nF
10nF
COMP2 SS2
FREQ
COMP1 SS1
10nF
22k 2.4nF
08143-081
fSW = 300kHz
Figure 81. Application Circuit for 3 A/1 A Outputs
8.2k
VIN = 3.3V 10 100k 1F
VDD
100k EN1 VIN1 VIN2 VIN3 PGOOD1 SW1 SW2 1H
12.1k 8.06k
EN2 22F PGOOD2 VOUT2 = 1.4V, 2A
12.1k 16.2k
VIN4 VIN5 VIN6 PGOOD2 SW3
22F PGOOD1 VOUT1 = 1.0V, 2A 100F
1H
ADP2114
SW4 PGND3 PGND4 FB2 V2SET
47F
PGND1 PGND2 FB1 V1SET 82k
82k SYNC 22k 560pF 10nF
OPCFG
FREQ
SCFG
GND
SYNC/CLKOUT COMP1 COMP2 SS1 SS2
10nF
33k 390pF
08143-082
fSW = 1.2MHz
Figure 82. Application Circuit for Adjustable Outputs
Rev. 0 | Page 34 of 40
4.7k
27k
ADP2114 POWER DISSIPATION, THERMAL CONSIDERATIONS
Power dissipated by the ADP2114 dual switching regulator is a major factor that affects the efficiency of the two dc-to-dc converters. The efficiency is given by
Efficiency = POUT x 100% PIN (21) Transition losses occur because the P-channel power MOSFET cannot be turned on or off instantaneously. The amount of transition loss is calculated by PTRAN = VIN x IOUT x (tRISE + tFALL) x fSW (26) where tRISE and tFALL are the rise time and the fall time of the switching node, SW. In the ADP2114, the rise and fall times of the switching node are in the order of 5 ns. The power dissipated by the regulator increases the die junction temperature, TJ, above the ambient temperature, TA. TJ = TA + TR (22) where the temperature rise, TR, is proportional to the power dissipation in the package, PD. The proportionality coefficient is defined as the thermal resistance from the junction of the die to the ambient temperature. TR = JA x PD (23) (28) where JA is the junction-ambient thermal resistance (34C/W for the JEDEC 1S2P board, see Table 2). When designing an application for a particular ambient temperature range, calculate the expected ADP2114 power dissipation (PD) due to conductive, switching, and transition losses of both channels by using Equation 24, Equation 25, and Equation 26 and estimate the temperature rise by using Equation 27 and Equation 28. The reliable operation of the two converters can be achieved only if the estimated die junction temperature of the ADP2114 (Equation 27) is less than 125C. Therefore, at higher ambient temperatures, reduce the power dissipation of the system. Figure 83 provides the power derating for the elevated ambient temperature at different air flow conditions. The area below the curves is the safe operation area for ADP2114 dual regulators.
2.2 2.0
MAXIMUM POWER DISSIPATION (W)
where: PIN is the input power. POUT is the output power. Power loss is given by PLOSS = PIN - POUT. The power loss of the step-down dc-to-dc converter is approximated by PLOSS = PD + PL where: PD is the power dissipation on the ADP2114. PL is the inductor power losses. The inductor losses are estimated (without core losses) by PL IOUT2 x DCRL where: IOUT is the dc load current. DCRL is the inductor series resistance. The ADP2114 power dissipation, PD, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. The power switch conductive losses are due to the output current, IOUT, flowing through the PMOSFET and the NMOSET power switches that have internal resistance, RDSON. The amount of conductive power loss is found by PCOND = [RDSON-P x D + RDSON-N x (1 - D)] x IOUT2 where the duty-cycle, D, = VOUT/VIN. Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by PSW = (CGATE-P + CGATE-N) x VIN2 x fSW where: CGATE-P is the PMOSFET gate capacitance. CGATE-N is the NMOSFET gate capacitance. (25) (24)
(27)
AIR VELOCITY = 500 LFM AIR VELOCITY = 200 LFM
1.8 1.6 1.4 1.2
1.0 AIR VELOCITY = 0 LFM 0.8 0.6 0.4 0.2 85 100 115
08143-083
0 70
AMBIENT TEMPERATURE (C)
Figure 83. Power Dissipation Derating (JEDEC 1S2P Board)
Rev. 0 | Page 35 of 40
ADP2114 CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential in obtaining the best performance from each channel of the ADP2114. Poor circuit layout degrades the output ripple and regulation, as well as the EMI and electromagnetic compatibility performance. For optimum layout, refer to the following guidelines: * Use separate analog and power ground planes. Connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to analog ground. In addition, connect the ground references of power components, such as input and output capacitors, to power ground. Connect both ground planes to the exposed pad of the ADP2114. Place the input capacitor of each channel as close to the VINx pins as possible and connect the other end to the closest power ground plane. For low noise and better transient performance, a filter is recommended between VINx and VDD. Place a 1 F, 10 low-pass input filter between the VDD pin and the VINx pins, as close to the GND pin as possible. Ensure that the high current loop traces are as short and as wide as possible. Make the high current path from CIN through L, COUT, and the power ground plane back to CIN as short as possible. To accomplish this, ensure that the input and output capacitors share a common power ground plane. In addition, make the high current path from the PGNDx pin through L and COUT back to the power ground plane as short as possible. To do this, ensure that the PGNDx pin of the ADP2114 is tied to the PGND plane as close as possible to the input and output capacitors (see Figure 84). Connect the ADP2114 exposed pad to a large copper plane to maximize its power dissipation capability. Thermal conductivity can be obtained using the method described in JEDEC specification JESD51-7. * Place the feedback resistor divider network as close as possible to the FBx pin to prevent noise pickup. Try to minimize the length of the trace connecting the top of the feedback resistor divider to the output while keeping away from the high current traces and the switch node, SWx, that can lead to noise pickup. To reduce noise pickup, place an analog ground plane on either side of the FBx trace and make it as small as possible to reduce the parasitic capacitance pickup.
VIN 1F 10 GND GND VDD VINx CIN L COUT VOUT LOAD SWx
*
*
ADP2114
PGNDx
*
FBx
08143-084
Figure 84. High Current Traces in the PCB Circuit
*
Rev. 0 | Page 36 of 40
ADP2114 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30 12 MAX
9
0.25 MIN 3.50 REF
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 85. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP2114ACPZ-R7 2 ADP2114-2PH-EVALZ2 ADP2114-EVALZ2
1 2
Temperature Range 1 -40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Single output, dual-phase interleaved, 1.2 V at 4 A, 1.2 MHz switching frequency, forced PWM Dual output, 3.3 V at 2 A and 1.8 V at 2 A, 600 kHz switching frequency, pulse skip enabled
Package Option CP-32-2
011708-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Ordering Quantity 1,500
Operating junction temperature is -40C to +125C. Z = RoHS Compliant Part.
Rev. 0 | Page 37 of 40
ADP2114 NOTES
Rev. 0 | Page 38 of 40
ADP2114 NOTES
Rev. 0 | Page 39 of 40
ADP2114 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08143-0-7/09(0)
Rev. 0 | Page 40 of 40

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